Search results for "network [detector]"
showing 10 items of 496 documents
A measurement-based study on the correlations of inter-domain Internet application flows
2014
Internet traffic characterization has a profound impact on network engineering and traffic identification. Existing studies are often carried out on a per-flow basis, focusing on the properties of individual flows. In this paper, we study the interaction of Internet traffic flows and network features from a complex network perspective, focusing on six types of applications: P2P file sharing, P2P stream, HTTP, instant messaging, online games and abnormal traffic. With large-volume traffic flow records collected through proprietary line-speed hardware-based monitors, we construct flow graphs of these different application types. Based on the flow graphs, we calculate the correlation coefficie…
An efficient distributed algorithm for generating and updating multicast trees
2006
As group applications are becoming widespread, efficient network utilization becomes a growing concern. Multicast transmission represents a necessary lower network service for the wide diffusion of new multimedia network applications. Multicast transmission may use network resources more efficiently than multiple point-to-point messages; however, creating optimal multicast trees (Steiner Tree Problem in networks) is prohibitively expensive. This paper proposes a distributed algorithm for the heuristic solution of the Steiner Tree Problem, allowing the construction of effective distribution trees using a coordination protocol among the network nodes. Furthermore, we propose a novel distribut…
Multiprocessor SoC Implementation of Neural Network Training on FPGA
2008
Software implementations of artificial neural networks (ANNs) and their training on a sequential processor are inefficient because they do not take advantage of parallelism. ASIC and FPGA implementations employ specific hardware structures to exploit parallelism in order to improve processing speed; however, optimizing resource usage requires the use of fixed-point arithmetic, thereby losing precision, and the final system is restricted to a particular network topology. This paper presents a mixed approach based on a multiprocessor system-on-chip (SoC) on a FPGA. The use of software-driven embedded microprocessors with custom floating-point extensions for ANN related functions allows for gr…
A Communication-Aware Topological Mapping Technique for NoCs
2008
Networks---on---Chip (NoCs) have been proposed as a promising solution to the complex on-chip communication problems derived from the increasing number of processor cores. The design of NoCs involves several key issues, being the topological mapping (the mapping of the Intellectual Properties (IPs) to network nodes) one of them. Several proposals have been focused on topological mapping last years, but they require the experimental validation of each mapping considered. In this paper, we propose a communication-aware topological mapping technique for NoCs. This technique is based on the experimental correlation of the network model with the actual network performance, thus avoiding the need…
Domain-Knowledge Optimized Simulated Annealing for Network-on-Chip Application Mapping
2013
Network-on-Chip architectures are scalable on-chip interconnection networks. They replace the inefficient shared buses and are suitable for multicore and manycore systems. This paper presents an Optimized Simulated Annealing (OSA) algorithm for the Network-on-Chip application mapping problem. With OSA, the cores are implicitly and dynamically clustered using knowledge about communication demands. We show that OSA is a more feasible Simulated Annealing approach to NoC application mapping by comparing it with a general Simulated Annealing algorithm and a Branch and Bound algorithm, too. Using real applications we show that OSA is significantly faster than a general Simulated Annealing, withou…
Novel Three-Phase Multi-Level Inverter with Reduced Components
2019
A new multilevel converter topology is proposed in this paper. Low component count and compact design are the main features of the proposed topology. Furthermore, the proposed converter is a capacitor-, inductor-, and diode-free configuration, allowing reducing the converter footprint, increasing the lifetime and simplifying the control strategy. Further, a comparative study is carried out to highlight the merits of the proposed circuit as compared to existing multilevel topologies. Finally, simulation results for the three-level version using different modulation strategies are presented.
A Kalman Filter Approach for Distinguishing Channel and Collision Errors in IEEE 802.11 Networks
2008
In the last years, several strategies for maximizing the throughput performance of IEEE 802.11 networks have been proposed in literature. Specifically, it has been shown that optimizations are possible both at the medium access control (MAC) layer, and at the physical (PHY) layer. In fact, at the MAC layer, it is possible to minimize the channel waste due to collisions and backoff expiration times, by tuning the minimum contention window as a function of the network congestion level. At the PHY layer, it is possible to improve the transmission robustness, by selecting a suitable modulation/coding scheme as a function of the channel quality perceived by the stations. However, the feasibility…
SoC-Based Implementation of the Backpropagation Algorithm for MLP
2008
The backpropagation algorithm used for the training of multilayer perceptrons (MLPs) has a high degree of parallelism and is therefore well-suited for hardware implementation on an ASIC or FPGA. However, most implementations are lacking in generality of application, either by limiting the range of trainable network topologies or by resorting to fixed-point arithmetic to increase processing speed. We propose a parallel backpropagation implementation on a multiprocessor system-on-chip (SoC) with a large number of independent floating-point processing units, controlled by software running on embedded processors in order to allow flexibility in the selection of the network topology to be traine…
Improving topological mapping on NoCs
2010
Networks-on-Chip (NoCs) have been proposed as an efficient solution to the complex communications on System-on-chip (SoCs). The design flow of network-on-chip (NoCs) include several key issues, and one of them is the decision of where cores have to be topologically mapped. This thesis proposes a new approach to the topological mapping strategy for NoCs. Concretely, we propose a new topological mapping technique for regular and irregular NoC platforms and its application for optimizing application specific NoC based on distributed and source routing.
A Clustering Approach for Improving Network Performance in Heterogeneous Systems
2000
A lot of research has focused on solving the problem of computation-aware task scheduling on heterogeneous systems. In this paper, we propose a clustering algorithm that, given a network topology, provides a network partition adapted to the communication requirements of the applications running on the machine. Also, we propose a criterion to measure the quality of each one of the possible mappings of processes to processors based on that network partition. Evaluation results show that these proposals can greatly improve network performance, providing a basis of a communication-aware scheduling technique.